The invention relates generally to memory devices and more particularly to driving ferroelectric capacitors within an array of ferroelectric random access memory cells.
There are a number of different types of integrated memory technologies. In a particular application, the selection of the type of memory will depend upon the requirements of the application. It is typical to use dynamic random access memory (DRAM) for dense storage of data where periodic memory refreshing is not an issue, while static random access memory (SRAM) is best suited for small but fast data storage and data retrieval where the large cell size of SRAM is acceptable. Flash memory provides nonvolatile storage of data, so that the data will still be available after power has been terminated. Selecting the memory technology on the basis of the application is more difficult when the needs occur within the same integrated circuit chip, such as within a system on a chip (SOC) design. One difficulty is the different memory technologies require different fabrication steps and specialized processes to individually maximize their performances.
One solution to the difficulties that arise when there is a desire to use the advantages of all three memory technologies (i.e., DRAM, SRAM, and Flash) within a single integrated circuit chip is to use the memory technology referred to as ferroelectric random access memory (FeRAM). FeRAM provides high data density, like DRAM, does not require a periodic memory refresh, unlike DRAM, and retains data when power is terminated, similar to Flash memory.
With reference to FIG. 1, a portion of a FeRAM array 10 is shown as including four memory cells 12, 14, 16 and 18. Within the FeRAM array, the memory cells are arranged in rows and columns. Merely by example, there may be 512 rows and 1024 columns of memory cells. Each FeRAM memory cell includes a pass transistor 20 and a ferroelectric capacitor 22. As is well known in the art, data storage in a ferroelectric capacitor 22 is through charge polarization to a xe2x80x9c0xe2x80x9d or a xe2x80x9c1xe2x80x9d state. In the orientation shown in FIG. 1, the bottom electrode of the ferroelectric capacitor 22 is referred to as the plate electrode. Plate lines (PL) 24 and 26 link the plate electrodes of each capacitor within a row. Similarly, word lines (WL) 28 and 30 couple all of the pass transistor gates of the same row. Bit lines (BL) 32 and 34 connect all of the corresponding source/drains of a particular column, so that data can be written into the ferroelectric capacitors. As one example, in order to polarize the ferroelectric capacitor 22 of the first memory cell 12 to a xe2x80x9c0xe2x80x9d state, the pass transistor 20 of that cell is activated via the first word line 28, while the corresponding bit line 32 is at xe2x80x9c0xe2x80x9d and the appropriate plate line 24 is set at xe2x80x9c1.xe2x80x9d On the other hand, to polarize the same ferroelectric capacitor 22 of the memory cell 12 to a xe2x80x9c1xe2x80x9d state, the word line 28 activates the pass transistor, the bit line 32 is forced to a xe2x80x9c1xe2x80x9d and the appropriate plate line 24 forces a xe2x80x9c0xe2x80x9d to the plate electrode of the capacitor. In a read operation, the plate electrode of the ferroelectric capacitor is pulsed xe2x80x9chighxe2x80x9d and the capacitor will dump the polarization charge associated with a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d through the memory cell pass transistor onto the bit line.
One issue in the design of a FeRAM array 10 is the selection of a plate-line architecture for driving the plate lines 24 and 26. As one possibility, a global plate line driver may be connected to all of the plate lines, so that the rows share the same connection. This global plate line architecture is represented in FIG. 2, which shows a single driver 36 connected to 512 rows. The advantage of the architecture is that the single driver 36 does not require a large amount of chip real estate, so that the required area efficiency is relatively high. A disadvantage is that at any one time there is one active row and 511 unselected rows that nevertheless contribute to the total capacitive load. The resulting relatively high capacitive load slows the rise and fall times of the plate line signal. Thus, the speed of the FeRAM array must be slowed accordingly. Another disadvantage is that since all connected memory cells experience disturb pulses even when they are unselected, the plate electrode of every ferroelectric capacitor within the array will recurringly experience the disturb pulses as the plate driver 36 is cycled.
An alternative plate drive architecture is shown in FIG. 3. In this segmented architecture, there is a single global plate line driver 38, but every local plate line (LPL) is connected to the driver through a transmission gate 40. Typically, the transmission gate is an NMOS device (n-channel metal oxide semiconductor device), with the global plate driver 38 being a CMOS device (complimentary metal oxide semiconductor device). The advantage of the architecture of FIG. 3 relative to the architecture of FIG. 2 is that the use of the transmission gates reduces the capacitive load on the global plate line driver 38, so that the operational speed of the memory array may be increased. A disadvantage is that the NMOS transmission gates require voltage boosting at their transistor gates in order to overcome the threshold of the NMOS device. As the desire for low voltage circuitry increases, this voltage boosting requirement increases in its importance. Another concern is that unselected bit lines will be allowed to xe2x80x9cfloatxe2x80x9d electrically, unless additional circuitry is used to tie unselected lines to electrical ground.
Another plate line architecture is represented in FIG. 4. In this architecture, each row of a ferroelectric memory array has a separate plate line driver 42. The drivers may be NMOS devices that require the voltage boost described with reference to FIG. 3. Thus, the use of the architecture in low-voltage applications is difficult. Moreover, the large number of drivers reduces the area efficiency of the memory array.
While the use of transmission gates or plate line drivers is not described, an alternative arrangement of connecting plate electrodes in a FeRAM memory array is set forth in U.S. Pat. No. 6,314,018 to Pxc3x6chmxc3xcller. Specifically, the patent describes an arrangement in which all of the plate electrodes of more than one word line row (or alternatively more than one bit line column) are connected to form a plate line segment.
The availabilities of the different prior art architectures allow a FeRAM memory array designer to select an architecture on a basis of a variety of factors, including available chip real estate and the target supply voltage (e.g., low-voltage application). However, each architecture also has disadvantages. What is needed is a FeRAM integrated circuit design and plate drive method which enable low-voltage, area-efficient implementations and which control the capacitive load placed on plate drivers, so that the integrated circuit may be operated at a relatively fast speed.
An integrated circuit device includes n lines by m lines of memory cells that are grouped with respect to common connections to plate electrodes of ferroelectric capacitors. Each group includes shared connections to ferroelectric capacitors of more than one of the n lines and more than one of the m lines. In one embodiment, the n lines are rows of memory cells and the m lines are columns of the memory cells. The multi-row, multi-column grouping of plate line connections enables greater flexibility with regard to the selection of a plate line drive scheme that satisfies both voltage-related requirements and area-related limitations.
While each group of plate line connections links ferroelectric capacitors of more than one column and more than one row, each group typically includes less than all of the columns and less than all of the rows. The selection of the number of columns and the number of rows within a group is based upon factors that include the total numbers of rows and columns and the intended type of plate line drivers. CMOS plate line drivers require a greater amount of chip real estate than is required by a pass transistor (e.g., an NMOS transistor). In the FeRAM design in accordance with the invention, there is a trade off between selecting large groups in order to minimize the number of required CMOS plate line drivers and selecting small groups that do not include a number of inactive rows for every active row within a group, since all rows of a plate line group will contribute to the capacitive load imposed upon the associated driver. As an example, an array having 512 rows may have plate line groups consisting of 32 rows each, so that there will be at least 16 (=512/32) plate line groups. If each group includes less than the total number of columns, the total number of plate line groups will be a multiple of 16. For example, if there are 1024 columns and each group includes 64 columns, the FeRAM array will be 16 groups wide by 16 groups high.
As a first aspect of the invention, the grouping of plate lines enables the use of CMOS plate line drivers. While such drivers require a significant amount of area compared to NMOS transmission transistors, the plate line grouping allows the total number of CMOS drivers to be controlled. Moreover, the capacitive load per plate line is largely reduced, because a single plate line driver only needs to drive the cells of one active row and a relatively small number of cells on inactive rows (e.g., 31 rows). Since the load of an inactive row is approximately one percent of the load of the active row, the capacitive load upon a particular CMOS driver is manageable. In addition to the CMOS driver, each plate line group may be operatively associated with a separate decoder, while the overall circuitry is maintained within the area-related limitations of the integrated circuit chip. The use of CMOS drivers rather than NMOS eliminates the need for a boosted gate voltage in order to drive the plate voltage to the full supply level. Consequently, low-voltage applications of the architecture result in lower power and less gate oxide stress.
Thus, in accordance with the first aspect of the invention, CMOS drivers are used in a one-to-one correspondence with groups of plate lines. A plate line group may be associated with 32 word line rows. There may also be a one-to-one correspondence between the plate line drivers and decoders, such as NAND gate decoders. Each plate line group may extend through all of the columns, or may be limited to only a segment of the bit line columns. On the other hand, in accordance with a second aspect of the invention, the selection of a plate line driver is not limited to CMOS circuitry, but plate electrodes of the ferroelectric capacitors are interconnected on the basis of a partial group of rows and a partial segment of columns. The division of plate electrode connectivity based upon both row grouping and column segmenting may provide significant advantages in some applications, even when CMOS plate line drivers are not used.